JaguarRoute

Observations From Our Benchmarks

The framework of routing technology: global routing, pin assignment, and detailed routing has been used sequentially in the EDA industry for a long time. Our benchmarks show the vulnerability of major routers in the area of "scalable performance". The four major EDA companies may need to consider integrating these three sub-modules into a simultaneous process, or discover other innovations, to maintain their leadership in the area of IC routing.

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Due to complexity of the IC design process, it is necessary to use a “divide-and-conquer” scheme, where the process is divided into a few sequential components, namely, front-end logic synthesis and back-end physical synthesis. The latter one is further divided into floor planning, placement, global routing, pin assignment, detailed routing components. The common practice is for each component to use the output of the previous component as the input and attempt to generate the best output for the next component. The drawback of this flow is quite obvious: the input of a component in some way is dependent upon the output of the same component. In this situation we are forced to use some estimation for the execution of each component. Because of the nature of estimations, being imprecise, either too optimistic or too pessimistic, the issues of closure of timing, signal integrity, routing, or area is accumulated and occurs at the last component, detailed routing. To solve the problem, it is not uncommon that a few iterations of this flow in both directions will be conducted before a satisfactory result is reached. Althought such complications are not desired, they are common practice in the current industry.